Design of Fused Add-Multiply Operator using Modified Booth Recoder for Fast Arithmetic Circuits

Abstract

Background: In Digital Signal Processing (DSP) the complex arithmetic instructions are mostly used. The decoding of these instructions usually takes more time in many applications. Methods: The objective of this research work mainly focused on the delay reduction by decreasing the partial products with the help of higher radix booth recoder. The booth recoder plays a key role in fused add-multiply operation for partial product generation. Findings: The proposed fused add multiply unit reduces the delay by reducing the number of partial products which is very useful for fast arithmetic circuits. The fused add-multiply units are simulated in Xilinx® 14.3 ISE in Virtex-5 environment and synthesized in Cadence® RTL Compiler and layout generated from Cadence® Encounter in 180nm technology. Conclusion: Based on experimental results, it is observed that the delay of the proposed method is reduced by 17.5% than the existing work.