Design of Full Adder Circuit Using Double Gate MOSFET

Abstract

This paper presents a design of a one bit full adder cell based on degenerate pass transistor logic (PTL) using Double Gate MOSFET. The design cell is degenerate 5-T XOR-XNOR module. This design has been compared with existing one-bit full adder cell based on degenerate pass transistor logic (PTL) designed using Single Gate MOSFET. In this paper, the proposed circuit has been analyzed for parameters like- power consumption and power delay product. The simulations of the proposed Full Adder have been performed using Tanner EDA Tool version 13.0. All the proposed design simulations are carried out at 45nm technology for various inputs like supply voltage, temperature and frequency. The decrease of 24% in power consumption has observed in proposed circuit. The results show a validity of double gate MOSFETs for designing for low power full adder circuit.