Design of DG MOSFET with Tri-Layered Strained Silicon Channel

Abstract

The Strained Silicon material concept gained their popularity since the last two decades. Along with that the double gate semiconductor on insulator (DGSOI) MOSFET also came into being with novel material based device being the requirement, hence a strain Silicon (s-Si) material DGSOI device has been developed to be the core of this work. A concise of three layers (s-Si/s-SiGe/s-Si) is deployed in channel region with varied thicknesses, and biaxial strain is thereby inducted. This leads to increase in the mobility of charge due to the inclusion of the strain mechanism in the silicon layers. The additional gate control provides better control of the channel region. Therefore, this new device with three-layered channel resulted in 59.6% enrichment in drain current for 22nm channel length, in comparison to 45nm channel length with minimum leakage current.