Design of Delay and Energy Efficient Low Voltage Dual Tail Comparator by Using Sleep Transistor

Abstract

AbstractThe need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. The analysis on the delay of the dynamic comparators is presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. The circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. In this paper, analysis of performances of conventional dynamic comparator, dual tail comparator, controlled dual tail comparator, sleep controlled dual tail comparator is carried out by using HSPICE A-2008.03 tool. Comparative analysis is carried out in terms of maximum sampling frequency, Delay and average Power of conventional dynamic comparator, dual tail comparator, controlled dual tail comparator, sleep controlled dual tail comparator.KeywordsDouble-tail comparatorDynamic clocked comparatorHigh-Speed Analog-to-Digital Converters (ADCs)Low-power analog design