Design of a Low Voltage low Power Double tail comparator in 180nm cmos Technology

Abstract

The need of analog to digital converters with ultra low power, area efficient and high speed is giving more chance to the use of dynamic regenerative comparators to maximize the speed and power efficiency. In this paper, an analysis on the delay and power of the dynamic comparators will be presented and based on the presented analysis, a new dynamic comparator is proposed, in which the conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Here by adding a few transistors, the power consumptions can be reduced drastically. Post–layout simulation using 180nm CMOS technology confirms the analysis results of the proposed dynamic comparator. INDEXTERMS: Double tail comparator, Power gating technique, Low-power analog design, Tanner EDA tool.