Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC

Abstract

Motivated by the upcoming upgrade of the ATLAS hybrid pixel detector, a new Front-End (FE) IC is being developed in a 130nm technology to face the tightened requirements of the upgraded pixel system. The main design goals are the reduction of material and a decrease in power consumption combined with the capability to handle the higher hit rates that will result from the upgraded machine. New technology features like the higher integration density for digital circuits, better radiation tolerance and Triple-Well transistors are used for optimization and the implementation of new concepts. A description of the ongoing design work is given, focusing more on the analog part and peripheral design blocks. I. ATLAS PIXEL UPGRADE SCHEDULE AND CONSEQUENCES ON FE-I4 SPECIFICATION The development of the FE-I4 pixel chip is motivated by planned upgrades to the ATLAS [1] pixel detector [3]. While upgrade plans are evolving, two distinct upgrades are expected based on the collider luminosity projections. The first upgrade, known as b-layer upgrade, is a new inner layer mounted on the beam pipe at a smaller radius and for luminosity a factor of 2 or 3 higher than present detector specifications. The second upgrade, known as Super-LHC, is on a longer time scale and it consists in the complete replacement of the ATLAS tracking detectors [2], for a luminosity 10 times higher than specified for the present one. The FE-I4 chip is aimed at inner layer use for the first upgrade, and outer layer use for the second upgrade, which is a natural fit because the hit rates for these two cases are comparable. The total area to be covered in the outer layers of the Super-LHC upgrade is about 4 times the total area of the present detector, and so reduction of manufacturing cost is an important requirement for FE-I4. With a potential smaller b-layer radius and a 2-3 times higher luminosity, the hit rate the FE-I4 will have to deal with will rise significantly. Simulations performed on the current FE-I3 architecture to study the influence of the increased hit rate, show that an unacceptable high number of relevant hits get lost because of pile up effects in the pixels and congestion in the double column data bus [5]. Hence a smaller pixel geometry of 50 × 250μm has been chosen to reduce the pixel cross section, having also a benefit on tracking resolution. In addition the digital pixel logic and the double column bus scheme have to be reorganized in a new architecture that is able to process the higher hit data volume. Serial links operating at 160MHz are needed for sending triggered hit data off-chip. Driven by the need to reduce material and bump-bonding cost, the overall chip size will be increased close to the technology’s limits to approximately 20.0× 18.6mm. In addition, the higher integration density the new technology offers allows to go to smaller peripheral chip area sizes which increases the active fraction from 74% in FE-I3 to almost 90% in FE-I4. Since bump bonding costs scale with the number of parts that have to be handled during the bonding process, both the bigger chip size and the use of fewer chips per module lower the manufacturing cost. Material reduction is also correlated to power consumption. To reduce the cable budget and at the same time limit the power losses in the cable, the current flowing through the supply lines has to be minimized. On that account 10μA current target for the analog readout chain has been defined per pixel. The same amount of current is dedicated to the digital pixel logic which is sufficient because with the new FE-I4 digital architecture concept the digital activity is much reduced (see section III.). Moreover different powering schemes like serial powering or divideby-two DC/DC conversion are under consideration to improve efficiency with respect to the conventional parallel powering approach. A comparison between some of the specifications of FE-I3 and FE-I4 is given in table 1. In the following sections the analog circuits that have been Table 1: Specification comparison between FE-I3 & FE-I4 target [3, 4] FE-I3 FE-I4 Pixel Size 50× 400μm 50× 250μm Pixel Array 18× 160 80× 336 Chip Size 7.6× 10.8mm 20.0× 18.6mm Active Fraction 74% 89% Analog Current 16μA/pixel 10μA/pixel Digital Current 10μA/pixel 10μA/pixel Analog Supply Voltage 1.6V 1.5V Digital Supply Voltage 2.0V 1.2V Data Rate 40Mb/s 160Mb/s