Design of Concurrent Error Detection Techniques for FFT implemented on FPGA platform

Abstract

Listen

Translate article

Fast Fourier Transform (FFT) is one of the popular techniques in digital signal processing applications. By use of FFT, we get the advantage of reduction in number of computations required over the traditional Discrete Fourier Transform (DFT). When implementing the complex FFT in SRAM based FPGA’s the major challenge is the soft errors. Soft errors leads to the modification of configuration memory bits which results in alteration of mapped circuit. For detecting the alteration of configuration memory bits in FPGAs, concurrent error detection(CED) techniques are used. Dual Modular Redundancy (DMR) is the most popular technique used for error detection whereas in-case of FFT, Parseval Sum of Squares (SoS) is the preferred technique for error detection. Analysis of these techniques show that DMR and SoS have good error detection capabilities but at cost of high resource usage. By utilizing some of the properties of FFT, it is possible to detect soft errors. These properties are nothing but form of input and output relations and involves less number of complex multiplications and additions which gives advantage of less resource usage. The proposed techniques along with DMR and FFT are implemented on FPGA and their resource usage is compared. Results show that proposed techniques required much less resources. Also the proposed techniques are tested for their error detection capabilities by injecting faults at FFT outputs.