Abstract

In this paper 65 nm CMOS technology based Low Noise Amplifier (LNA) circuit with four stages of cascaded Common Source (CS) amplifier is designed to operate in the frequency range of (57-86) GHz. The LNA circuit consists of feedback inductor and drain inductors to improve the gain performance and input matching. The design is modelled in ADS Software and simulated to study LNA performances such as Noise Figure (NF), gain, Third Order Intercept point (TOI or IIP3), stability and FOM. The simulated results show that the amplifier exhibits a power gain of 29.48 dB at (57-65) GHz, 28.18 dB at (71-76) GHz and 20.84 dB at (81-86) GHz. The estimated 3-dB bandwidth is 18 dB from (55-86) GHz. The noise figure is less than 6 dB between 55 GHz to 86 GHz. The 1 –dB compression is -14 dBm and IIP3 is -4 dBm. The power consumption is 27 mW under a 1V supply.

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