Design of CNTFET-based Ternary Logic circuits using Low power Encoder

Abstract

Ternary logic has received considerable attention in the past decade for its advantages of reduced chip area and reduced chip interconnect compared to traditional binary logic. Carbon Nanotube Field Effect Transistor (CNFET) technology is widely used to implement ternary logic due to it's variable threshold voltage. However, the existing designs using CNFET consume higher power compared to binary logic due to static power dissipation included in their designs. In this paper, alternative designs for Ternary Encoder are proposed with focus on reducing the power consumption. These designs use an additional <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Vdd/2$</tex> supply voltage to reduce static power dissipation and the Power Delay Product (PDP) of encoder. The encoder is used to implement a Ternary Half Adder(THA) and Ternary 1-digit Multiplier (TMUL) with the decoderless approach. The proposed encoder achieves 90% and 96 % reduction in power consumption for THA and TMUL respectively.