Design of CMOS Memristor Emulator and Logic Gates For Neuromorphic Circuits

Abstract

In this work, we have emulated the memristor characteristics using CMOS technology. Different topologies of the CMOS memristor have been realized. The design of an optimized memristor emulator circuit uses only three MOSFET transistors and a MOS cap. The proposed emulator exhibits similar nonlinear voltage-current characteristics and hysteresis as memristors. Previously developed memristor emulator circuits were complex because they required a large number of transistors and other blocks to achieve the desired memristor-like behavior. Our proposed memristor emulator will consume low power and have a small chip area. The memristor circuit simulation was performed using HSPICE at the 90nm CMOS technology node. The simulation result shows that the delay and power consumption in 4-NMOS-based and 1-NMOS/2-PMOS-based memristor emulators are lower than other existing emulator topologies. Furthermore, memristor emulator circuits have been used to realize the 2-input OR and 2-input AND gates. The development of CMOS based memristor emulator circuits and logic gates will pave the way for neuromorphic and machine learning circuits.