Abstract
Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. Multiplier is designed, considering the tradeoffs between low power and high speed. The bypassing multiplier is an improvement, over Braun multiplier which is one of the parallel array multiplier. The tradeoffs i.e. dynamic power and delay of the Bypassing multipliers can be reduced by using different adders. This paper presents a comparative study of 1-dimensional and 2-dimensional bypassing multipliers using different adders on basis of delay, area and power and for 4x4, 8x8 and 16x16 bits in FPGA Spartan – 3E using Xilinx 12.4 ISE and Synopsys respectively.
Highlights
Low power design has become a great concern in VLSI design in recent years
Using Design Vision Synopsys, the designs are synthesized for dynamic power and area as listed in Table 2 and 3
When implemented with carry select adder compared with other bypassing multipliers
Summary
Low power design has become a great concern in VLSI design in recent years. There exists a strong necessity to investigate techniques for lowering energy dissipation of devices, such as Digital Signal Processors(DSP). Digital multipliers are essential arithmetic blocks for many DSP applications: filtering, convolution, DCT, Fourier Transform, etc. It consumes almost 2/3 of the total power. Many prior digital multipliers were aimed at transition or switch reductions to reduce power dissipation as well. Many low-power multiplier designs can be found in the literature. A straightforward approach is to design a multiplier that consumes less power [1] as well as less hardware. Another way is through modifying the structure of full adder at circuit level, depending on number of input[4]. Figure 3. 4x4 Braun multiplier using Row Bypassing[4]
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