Comparative Study of High performance Braun’s Multiplier using FPGAs

Abstract

Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. With the advancements in technology, research is still going on to design a multiplier that consumes less power or has high speed or occupies less area or a combination of these in a single multiplier. This makes the multipliers to be used for high speed or low power VLSI applications. The Braun’s multiplier is one of the parallel array multiplier which is used for unsigned numbers multiplication. The dynamic power of the multiplier can be reduced by using the bypassing techniques. The delay can be reduced by replacing the ripple carry adder in the last stage by fast adders like Carry look ahead adder and Kogge stone adder. This paper presents a comparative study among different types of bypassing multipliers for 4*4, 8*8 and 16*16 bits and their architectural modifications using different FPGAs like Spartan – 3E, Virtex – 4, Virtex – 5 and Virtex – 6 Lower power using Xilinx 13.2 ISE tool from which we get the delay and the dynamic power and cell area reports are obtained using RTL Compiler from Cadence in 90 nm technology.