Design of AWC core using DCD iterations for MVDR beamformer

Abstract

This paper presents a hardware architecture using Dichotomous Coordinate Descent (DCD) iterations for Adaptive Weight Computation (AWC) in Minimum Variance Distortionless Response (MVDR) Beamformer. The objective of the proposed work is to achieve low latency and reduced area architecture for the AWC stage in MVDR Beamformer. The work investigates the computation of adaptive weight for 4,8,16 and 32 channels array beamformer. In order to improve the weight updating rate, the existing complex valued cyclic DCD hardware implementation is optimized to 2 clock cycles per iteration. Moreover, DCD algorithm implementation does not require any multiplication and division. The proposed work is implemented on FPGA platform, and the results are compared with state-of-art literature and conclude that the proposed architecture is suitable for MVDR Beamformer employed in high sampling rate applications like medical ultrasound imaging due to its occupancy of a moderate amount of resources and improved processing speed.