Abstract
Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely used in scientific computing and signal processing applications, but the complexity increases in hardware implementations of floating point units. In VLSI design architecture, many applications suffer in size of the components used in logical operations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction in size of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimize the area, a novel design of floating point processing element (FPPE) architecture is proposed in this work with a smaller number of logical components and registers. A partially folded arithmetic function architecture is modeled for the design of an infinite impulse response (IIR) filter using FPPE and implemented on a field programmable gate array (FPGA) with efficient area. FPGAs are widely used in the implementation of floating point computing modules due to the increase in gate density and embedded arithmetic cores. Synthesis results prove that the proposed design of the IIR filter provides efficient area compared with existing works. The modules are designed in Verilog and implemented on Xilinx FPGAs.
Highlights
Floating point arithmetic and logic units are a part of computer systems
field programmable gate array (FPGA) are used for the implementation of floating point arithmetic units because of their increased integration density compared with Application specific integrated circuits (ASICs) and provide increased computing speed [3,4,5,6]
Conclusion and future work This work proposed the design of floating point arithmetic units for signal processing applications
Summary
The requirements of floating point arithmetic have become very intense due to its dynamic range representation of real numbers compared to fixed point values. FPGAs are used for the implementation of floating point arithmetic units because of their increased integration density compared with ASICs and provide increased computing speed [3,4,5,6]. Recursive or infinite impulse response (IIR) filters depend on the past output results and have an infinite number of coefficients. These filters have feedback and nonlinear phase characteristics. In this work, floating point processing element (FPPE) architecture is designed to implement IIR filters on FPGAs with reduced number of registers and logical operations.
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