Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications

Abstract

Approximate computing is a promising technique for energy-efficient Very Large Scale Integration (VLSI) system design and best suited for error resilient applications, such as signal processing and multimedia. Approximate computing reduces accuracy, but still provides significant and faster results with low power consumption. It is attractive for arithmetic circuits. Four approximate subtractors are proposed based on the approximate computing at logic level using Karnaugh map (K-map) simplification. This paper deals with the design approach of various approximate subtractors and dividers for image processing to tolerate the minimal loss of quality. The proposed designs offer better error tolerant capabilities for image processing