Design of an Optimal Integer Frequency Synthesizer for 5 GHz Frequency at 45 nm CMOS Technology

Abstract

Design and optimal analysis of Frequency synthesizer using a phase-locked loop (PLL) have been illustrated in this paper. Here, the design and analysis of a frequency synthesizer are done using 45 nm CMOS technology on a Cadence platform. The design of the frequency synthesizer mainly consists of four blocks: a phase frequency detector, low-pass filter, a voltage controlled oscillator (VCO), and a frequency divider. This paper proposed an optimized design of frequency synthesizer to generate a frequency range from 5.15 to 5.3 GHz and give steady-state output power at that frequency which is 3 dbm through periodic steady-state (PSS) analysis. It provides excellent noise characteristics at the operating frequency, and the output noise that it gives at frequency 5.3 GHz is \(1.0298\,{\text {e}}^{-19}\) V/sqrt (Hz), and phase noise is −100 dBc/Hz at 1 MHz offset. In wireless communication, this frequency synthesizer is an essential building block which is used to generate a frequency range from a single frequency oscillator and is used in many modern communication applications such as radio receiver, television, walkie talkies, GPS system, radiotelephone, and CB radios.