Abstract
Digital Multiplier is a fundamental component in many digital signal processing (DSP) systems, which takes up the most part of the computational resources. As many DSP applications have an inherent tolerance for inexact computations, approximate multiplication is considered as an appropriate substitution to obtain energy-performance-accuracy tradeoffs, especially in those applications that require high energy-efficiency in computing. Meanwhile, reducing the supply voltage is proved to be an efficient way to further lower the total energy consumption. In this paper, a novel approximate 4-2 compressor and its circuit implementation is proposed for error-resilient multiplication with a low supply voltage. Simulation results indicate that the approximate multiplier with our proposed approximate 4-2 compressor consumes the least energy per operation with the same computational accuracy when compared with other multipliers for the operand length of 8 bits. It achieves 26.7% reduction on energy-delay product (EDP) when compared with the exact multiplication.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
