Chapter 8 - High-level Design Tools for Complex DSP Applications

Abstract

This chapter presents a system-level methodology of designing and synthesizing real-time digital signal processing (DSP) systems. Current hardware designs and implementations for DSP systems have a huge time gap between the development of algorithms for new DSP applications and their hardware implementation. The high level design and synthesis tools create application-specific DSP accelerators from high abstraction-level for complex DSP processing hardware, which greatly reduces the design cycle while still maintaining area and power efficiency. This chapter presents two high-level design methodologies: 1) C-to-RTL high-level synthesis (HLS) for ASIC/FPGA implementation of the DSP systems; and 2) System Generator for FPGA implementation of the DSP systems. In the case studies, we will present three complex DSP accelerator designs using high-level design tools: 1) Low-density parity-check (LDPC) decoder accelerator design using PICO C; 2) Matrix multiplication accelerator design using Catapult C; and 3) QR decomposition accelerator design using System Generator.