Abstract
The proposed 8-bit Flash ADC design does not require resistor ladder circuit and it can operate at Giga Hz range with concurrent bubble error correction of 2nd order. It consists of 28 − 1 comparators and two encoding blocks. First encoding block is a 1 — out of — N coder circuit and the second consists of NAND and NOR gates i.e. a simple binary encoder. Threshold Inverter Quantizer (TIQ) technique is used in designing the comparators. There are many issues in a Flash ADC, out of which bubble error is one. Correction of bubble error reduces the loss of bits and provides much better resolution. This design provides low power, high speed and high resolution.
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