Design of an Approximate Adder based on Modified Full Adder and Nonzero Truncation for Machine Learning

Abstract

This paper proposes a novel approximate adder based on a modified full adder that exploits AND-based bit-by-bit carry prediction and OR-based summation, and nonzero truncation scheme. The proposed adder design offers good tradeoff between the computation accuracy and hardware efficiency. When implemented in 32-nm CMOS technology, the proposed adder improves the area, power, and energy by up to 48.9%, 45.6%, and 45.4%, respectively, compared to existing approximate adders considered in this paper. Furthermore, our adder demonstrates excellent processing quality with remarkably reduced hardware resource when applied to image processing and machine learning applications.