Abstract

The design of a processing subsystem for a prototype data-flow computer being built at Manchester University is described. The machine architecture and underlying notation in which programs are expressed allow the exploitation of parallelism in program execution at the instruction level. The processing subsystem may thus be designed as a parallel array of processing elements with a modular input/output interface. Faster execution rates can be achieved by the addition of more processing elements, so that a conventional bit-slice architecture is sufficient for their construction. The implementation of the machine ordercode is considered, and the instruction times are used to assess the subsystem's performance. This should achieve an execution rate of 3.3 MIPS with an array of 15 processing elements.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.