Design of a Novel Digital Baseband for UHF RFID Tag

Abstract

This paper presents a novel low-power digital baseband for UHF RFID tag. The design is complied with a modified ISO 18000-6C protocol. In order to reduce the peak power, module-reuse and other advanced low power techniques are applied. And a novel baseband architecture is discussed, which fulfills the protocol functions and reduces power consumption. The whole tag chip, including digital baseband, RF/analog frontend and memory, has been taped out using TSMC 0.18um CMOS process. The chip area is 89234 um2 excluding test pads. Its power consumption is 11.63uw under 1.1v power supply.