Abstract
The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
Highlights
System on Chip (SoC) and System in Package (SiP) technologies provide a path for continued improvement in performance, power, cost and size at the system level without relying upon conventional CMOS scaling alone
This paper reports following new contributions for On-Chip SerDes Transceivers as compared to earlier published work:
Each double edge triggered flip flop (DETFF) is composed of two types of flip flops: first is a positive edge triggered flip flop and second is a negative edge triggered flip flop
Summary
System on Chip (SoC) and System in Package (SiP) technologies provide a path for continued improvement in performance, power, cost and size at the system level without relying upon conventional CMOS scaling alone.How to cite this paper: Jaiswal, N. and Gamad, R. (2015) Design of a New Serializer and Deserializer Architecture for OnChip SerDes Transceivers. These advances allow the number of integrated modules to grow much more rapidly on a single chip [1] or in a single package. These technologies will require a large number of parallel wiring nets and buses for interconnections as well as data communication between these modules. Serial link based designs have been used for decades in Off-Chip Communications because it offers many advantages over traditional parallel implementations including fewer pins, reduced space requirements, reduced complexity, lower power consumption, smaller connectors, lower electromagnetic interference, and better noise immunity [5] [6]. A similar problem exists for On-Chip communication in these new technologies mainly because of power and area overheads
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