Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps

Abstract

We present a cascaded chaotic system as a hardware-efficient way of elevating the entropy in the chaotic behavior of CMOS-based chaotic maps. The chaotic performance of the proposed scheme is evaluated using the bifurcation plot, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient. The improved entropy in the chaotic region benefits many security applications and is demonstrated experimentally in a new random number generator (RNG) design based on the proposed map. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), the proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise which renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded map, significantly low area and power overhead are achieved in the RNG design and it passes three statistical tests namely, NIST, Diehard, and TestU01.