Design of a low phase noise voltage-controlled oscillator for chip-scale cesium atomic clock

Abstract

The atomic clock based on the coherent population trapping (CPT) phenomenon is currently the only one that can realize miniaturization in principle. It's very necessary for the closed-loop locking of the CPT cesium atomic clock to provide a small size, low power consumption and low phase noise 4.596GHz (half of the cesium atomic ground-state hyperfine splitting frequency) voltage-controlled oscillator (VCO) as the microwave signal source. This paper describes the design of the VCO using the negative resistance analysis method. The parameters of the circuit are optimized using the transmission analysis method with a virtual ground. Simulations are carried out respectively in the time domain and frequency domain to evaluate the performance of the VCO. The size of the designed VCO is 7.8 mm by 7.7 mm. The test data show that the phase noise is −46.28dBc/Hz@300Hz and better than −43dBc/Hz@300Hz based on the requirements of the chip-scale atomic clock (CSAC) specified by the Defense Advanced Research Projects Agency, and the tuning sensitivity of the designed VCO is about 110MHz/V.