Design of a Low Noise Bias Generator for Multi-band RF CMOS Transceiver

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A low noise bias generator for RF CMOS transceiver is proposed and implemented. The bias generator consists of a bandgap reference(BGR) and a low dropout regulator(LDO). In RF transceiver, the bias blocks determining bias quantity and quality of the signal-processing circuits are separately placed near each signal block for noise performance and proper power dividing. Therefore, bias block design issues such as power consumption, noise and chip size should be considerd for multi-band RF CMOS transceiver which has various circuit blocks and chip area constraints. This paper describes a design procedure and techniques for a low noise bias generator. The proposed techniques allow good trade-off among chip size, noise and power consumption. The bias generator gives temperature compensated bandgap reference of 1.2V with mean temperature dependency of 5ppm/˚C for -25˚C to 75˚C. The LDO is able to drive max bias current of 15mA. The bias generator is implemented in a 0.18m RF CMOS technology with a size of 0.2×0.4mm2 and consumes a bandgap core current of 40A at 2.5V supply and works for a power supply down to 1.8V. Output noise level is below 30nV/√Hz at 100kHz. A CMOS VCO with the proposed bias generator has the phase noise difference of only 2.2dBc/Hz at 400kHz offset.