Design of a K-Band High-Efficiency Power Amplifier in 45 nm SOI CMOS Technology

Abstract

This paper presents a high efficiency K-band CMOS power amplifier (PA) in GlobalFoundries (GF) 45 nm SOI CMOS technology for 5 G applications. Compared with an ordinary two-stage PA, the PA uses a current-reused technique to enhance the power gain and efficiency within the frequency band. The resistance feedback structure of the power output stage improves the gain flatness and the output bandwidth, and reduces the matching components. The simulation results show that the output power (Pout) is more than 21.6 dBm from 18 to 27 GHz, while the small signal gain (S21) is more than 30.6 dB, the output 1 dB compression point (OP1dB) is 19.8 dBm and power-added efficiency (PAE) is 36.8%. With a 64-QAM LTE signal with 20-MHz bandwidth, adjacent channel leakage ratio (ACLR) is −31.2 dBc and the error vector amplitude(EVM) is less than − 26.7 dB at an average output power of 10.9 dBm. The chip area with pads is 0.75mm2, and consumes 15.1 mW from 2.4 V.