Design of a fast, low-level fault-tolerant protocol for Network on Chips

Abstract

Network on a chip (NoC) has been proposed to address the inefficiency of buses in the current System on Chips (SoC). However as the chip scales, the probability of errors is also increasing, thus, making fault tolerance a key concern in scaling chips. Transient faults are becoming a major cause of errors in a packet based NoC. A transient error can either corrupt the header or the payload of packet requiring a retransmission from the source. Due to retransmissions, packets arrive out of order at the receiver side. Complex reordering algorithms are required at the receiver side to organize packets before sending them to associated resource. This adds a major overhead as the storage and logic capabilities are limited on a chip. We therefore provide a low-cost, fast and reliable end-to-end protocol for NoC which does not require reordering of the packets at the receiver end. Our protocol performs bitwise logical operations using binary representation of the addresses for the buffers to handle packets, hence making it much faster than conventional algorithms. Furthermore, the protocol is equally applicable to both static as well as dynamic routing environments on a chip.