Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM

Abstract

A high-speed and low-power prepared and write sense amplifier (PWSA) is presented for magnetoresistive RAM (MRAM). The sense amplifier incorporates a writing circuit for MRAM bits switched via timing of precessional dynamics (~GHz speed) in a magnetic tunnel junction (MTJ). By combining read and write functions in a single power-efficient circuit, the PWSA allows for fast read and write operations while minimizing the bit error rate after data programming. The PWSA circuit is designed based on a 65 nm CMOS technology, and the magnetic dynamics are captured by a Verilog-A compact model based on macrospin behavior for MTJs. Using the preread and comparison steps in the data program operation, we are able to reduce write power consumption by up to 50% under random data input conditions. Furthermore, using the voltage-controlled magnetic anisotropy effect for precessional switching, more than 10× reduction of write power and transistor size both in the memory cell and the write circuit is achieved, compared with using the spin transfer torque effect. The circuit achieves 2 ns read time, 1.8 ns write time, and 8 ns total data program operation time (consisting of two read steps, one write step, and a pass/fail check step) using this PWSA concept, and a 2× larger sensing margin through the current feedback circuit.