Design of a dual-issue RISC-V processor

Abstract

A dual-issue 32-bit RISC-V processor is designed and reported. In order to evaluate the performance of the dual-issue processor, a single-issue processor based on the open source RISC-V instruction set architecture is first designed for reference and it is also the base of the dual-issue processor. The single-issue reference processor, which has a 5-stage pipeline, supports base integer instruction set, integer multiplication and division and compressed instructions, has passed the corresponding functional and compliance tests. The dual-issue processor extends the pipeline to dual-issue and introduces additional processing to solve data hazards in the pipeline. The evaluated result of the dual-issue processor shows that it has significant performance improvement than the single-issue processor.