A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation

Abstract

AbstractRISC-V is a free and open instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. RISC-V ISA enables a new phase in the field of processors through open standard association. The address of RISC-V is based on 32-bit and 64-bit variants. The essential RISC-V is a 32-bit integer instruction set defined as RV32I, which efficiently supports the operating system environments and also suits for the embedded system applications. In this paper, a survey is carried for 5-stage in-order pipeline implementation and ways to overcome pipelining hazards for structural hazards, data hazards, and control hazards on RISC-V processors. Being open-source and free, this is adopted in many commercial and academic research and projects.KeywordsRISC-VInstruction set architectureIn-order5-stage pipelineHazards