Design of a 9 GHz CMOS low noise amplifier using gain-enhanced technique

Abstract

In this article, a 9 GHz low noise amplifier (LNA) using gain-enhanced technique is presented. The compact and high-gain LNA with cascode topology is implemented in a standard 0.18-μm CMOS process. The gain-enhanced technique consists of two inductors in the common gate (CG) stage of the cascode configuration. The first inductor at the source terminal in the CG stage eliminates the parasitic effects caused by the parasitic capacitances of transistors at high frequencies. Moreover, the second inductor at the gate terminal in the CG stage achieves a negative resistance making a high gain characteristic of the amplifier. Finally, the measured small signal gain, noise figure and input P1dB at 9 GHz are 16.5 dB, 4.5 dB, and −15 dBm, respectively. The chip size of the compact LNA is 0.48 mm × 0.8 mm including all testing pads. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:479–481, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25778