Design of a 25000 gate ASIC using VHDL

Abstract

IEEE 1076 compatible VHDL (VHSIC Hardware Description Language) was used to create a behavioral model for a complex ASIC (application-specific integrated circuit) design. Specifically, VHDL was used in the development of the HTIU2000 Test-bus Interface Unit. The design process incorporated VHDL from the beginning of the design cycle; the behavioral description of the HTIU2000 was performed in VHDL from the beginning of the process, not converted to VHDL from another hardware description language. The behavioral model was successfully converted to a gate-level implementation in a standard cell library using some synthesis of the VHDL code. The part was fabricated and the behavior of the parts matched that of the VHDL model. The successful fabrication of the HTIU2000 chips, illustrates that VHDL and design synthesis can be used to design complex ASICs. >