Design of 3:1 multiplexer standard cell

Abstract

A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 /spl mu/m CMOS standard cell library has been developed. The new cell shows a propagation delay of /spl sim/780 ps and dissipates 5.2 /spl mu/W/MHz.