Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi- $V_{\rm th}$ Transistors

Abstract

We proposed a multi-Vth transistor design for a body-biasing scheme to control threshold voltage Vth variation and power consumption for the 65-nm node and beyond. One of the biggest barriers in applying the body biasing to multi-Vth transistors that have a different body-biasing sensitivity was solved by using a Hf-based gate dielectric work-function modulation combined with a careful channel design. The body-biasing sensitivities for multi-Vth transistors were successfully equalized, and the sensitivity is independent of the original Vth. By using the body biasing with the optimal transistor design, die-to-die Vth variation has been efficiently suppressed even for dies with multi-Vth transistors. As a result, both 50% total Vth variation reduction and 1/50 static random access memory standby current have been achieved. This design scheme can guarantee excellent performance for future low power applications because of its simplicity and its bulk-design compatibility.