Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Abstract

Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si3N4, HfO2), and hybrid dual-k (Air + Si3N4) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO2) spacer gives a higher switching ratio (ION/IOFF) in the order of ~107, subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO2) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si3N4) outperforms in terms of gain (AV) and output resistance ( R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m 2 , g m 3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.