Abstract
In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software.
Highlights
In today’s world, the information technology is depending on semiconductor based electronics
The sub threshold leakage current ISUB has a greater contribution for power dissipation than the other leakage current in CMOS technologies
Where S denotes the sub threshold swing parameter .It is highly desirable that S should be small as possible because it is going to determine the amount of voltage swing necessary to switch ON and OFF the MOSFETIncrease in temperature results in larger S value this in turn increase the OFF
Summary
In today’s world, the information technology is depending on semiconductor based electronics. The first transistor was invented in 1948, there will be a tremendous growth in semiconductor industry. There are two major fields which are benefited by the growth of semiconductor industry, are semiconductor based memories and microprocessors. The performance has improved by this technological advancement parallel the device density increases. The power dissipation in integrated circuit(IC) depending on different operating modes of the circuit .first one is during active mode of operation the dynamic power is dominating. Second one is two primary leakage sources the active and standby leakage component. Plementation of 8T circuit in array structure.
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