Abstract
In this paper, a design for testability methodology for a multi-mode navigation baseband SoC chip was presented, merging the various DFT techniques including boundary scan, MBIST, and full scan based ATPG. Implementation the technology of pattern compression was introduced in detail. Test results showed that this strategy is feasible, and meets the requirement of engineering applications. The test coverage of this chip is 97.53%, in the condition that, almost 30-fold test pattern compression is achieved
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