Design for testability — a review of advanced methods

Abstract

In an attempt to curtail the almost exponential growth in testing cost as circuit complexity increases, attention has focussed over the past decade on design for testability (DFT). Although DFT techniques reduce the testing cost there is a penalty to be paid in terms of the overheads incurred through their use. The paper first presents several recently evolved hybrid techniques that combine several DFT techniques with the objective of maximizing the advantages of each method whilst minimizing their overheads. It has been predicted that, as a result of the decrease in device size through the improvements in fabrication technology, the incidence of intermittent faults will increase. Current test strategies are not generally suitable for detecting this type of fault, and the paper discusses the application of concurrent circuit testing techniques, employing information redundancy, to the problem. The vast number of DFT techniques available, each with its own advantages and disadvantages, means that the designer faces a formidable task in selecting the best technique for a particular circuit. Several expert systems developed to analyse the circuit and suggest the most appropriate technique are presented. This approach has been developed further by integrating the expert system into a silicon compiler environment which ensures that the circuit is testable by virtue of its construction.