Design for security test on cryptographic ICs for design-time security evaluation

Abstract

Cryptographic ICs are facing a serious threat of fault injection attacks. However, the security test nowadays is still sample test instead of volume test, exploiting workload statistics and experiences as qualitative indexes. This paper proposes a design for test method, to facilitate fast and automatic security test of cryptographic ICs. First we identify the sensitive registers crucial to the fault injection, and the secret key related registers are carefully isolated out of the marked registers. Next, the scan chains are inserted onto the marked registers and the test pattern is generated. Finally, the cryptographic IC is evaluated in test mode with fault injection simulation, and the simulation result will be compared to the golden reference pattern. Any inconsistency indicates the crypto chip will fail in the security test. The reported faulty chains and cells could locate the weaknesses accurately. The case study on a CRT-RSA implementation proves the feasibility of the proposed method, with negligible hardware overhead. The method can be easily extended to other cryptographic algorithms.