Design for security test against fault injection attacks

Abstract

A design-for-test method on cryptographic integrated circuits against fault injection attacks is proposed. The method involves identifying the sensitive registers, inserting the scan chain accordingly and functioning in test mode during the fault injection security test. The transient errors caused by fault injection can be quickly and efficiently revealed for security evaluation, but the errors cannot be exploited by the attackers to compromise the secret keys, due to isolation of the secret key related registers. The experimental result on a Chinese remainder theorem-RSA implementation verifies the feasibility of the proposed method with the area overhead as low as 2.5%. The method is able to facilitate a fast and volume test.