Design for Robust Testability

Abstract

If a test set exists for a CMOS circuit which detects all the stuck-open faults in it in the presence of arbitrary circuit delays and timing skews, then the circuit is said to be robustly testable. We saw earlier in Chapter 2 that dynamic CMOS circuits, such as domino CMOS and cascode voltage switch logic circuits, are always robustly testable. However, this is not true for all static CMOS circuits. In this chapter, procedures for designing robustly testable static CMOS circuits will be discussed. Generally, the circuits are designed to be robustly testable with respect to single stuck-open faults. However, we will also discuss a method which guarantees robust testability with respect to multiple faults.KeywordsTest VectorpMOS TransistorCMOS CircuitNAND GateDelay FaultThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.