Design Features of Compliant Packages and Their Impact on Reliability

Abstract

Abstract It is well-known that the main cause of mechanical failure in electronic packages is due to the difference in the Coefficients of Thermal Expansion (CTE) of the silicon and the organic board. There are many packaging technologies that try to overcome this limitation; ranging from making curved connection pins (gull-wing leads) from the package to the board, as in the case of Thin Small Outline Package (TSOP), to using hard epoxy to rigidly adhere the die to the board as in the case of flip-chip packages. This paper illustrates a compliant packaging concept that minimizes the effect of the CTE mismatch between the silicon die and the board. A summary of different packaging techniques that address the CTE mismatch problem is presented. From this summary, it is apparent that many of these techniques do not provide as high reliability as the compliant packages do, especially when the electrical connections from the package to the board (solder balls) are present directly under the silicon die as in the case of chip scale packages. As the compliant package isolates the effect of the silicon die from the substrate, the silicon has some motion relative to the substrate. This means that the interconnections from the silicon to the substrate must be designed to withstand this motion. Hence the design of these interconnections is key to maximizing the reliability of the compliant packages. A detailed design and reliability analysis of compliant packages for different applications is presented. The design highlights the main parameters that have an effect on reliability of the package. Reliability simulation and analysis using finite element techniques is presented for different designs to highlight the key parameters that govern the reliability of compliant packages. Finally, reliability testing data is presented for different packages.