Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine

Abstract

A feasibility study for implementing the advanced encryption standard (AES) encryption algorithm in hardware achieving 500 Gbits/s is presented. Iterative processing cores are used to achieve the 500 Gbits/s. The throughput of the iterative cores is enhanced by processing four different flows of data in parallel. This does not increase the latency which is highly beneficial in the context of block cipher modes. The iterative core field-programmable gate array (FPGA) synthesis results in a throughput of 4.9 Gbits/s for an area of 6310 look-up tables (LUTs) outperforming several other contributions results. Several instances of the iterative processor are compared with pipelined architectures. The results have shown that for most implementations the group of iterative processors also outperforms pipelined architectures. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution. The obtained architecture is highly modular and scalable. The key schedule generation is decoupled from the cipher/decipher engine. Block cipher mode datapath design is presented. The task of scheduling the different flows onto different iterative cores is realised through the use of a distributed scheduling architecture that implements a de-facto load balancing.