Design, Fabrication, and Calibration of a Piezoresistive Stress Sensor on SOI Wafers for Electronic Packaging Applications

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents the development of a piezoresistive stress sensor fabricated on silicon-on-insulator (SOI) wafers for measurement of electronic packaging stress at high temperature. The sensor consists of a series of sensor elements and calibration elements. The sensor elements comprise a 0<formula formulatype="inline"><tex Notation="TeX">$^{\circ}$</tex></formula>–90<formula formulatype="inline"><tex Notation="TeX">$^{\circ}$</tex></formula> p-type piezoresistor pair and a <formula formulatype="inline"><tex Notation="TeX">$\pm {\hbox {45}}^{\circ}$</tex></formula> n-type piezoresistor pair for stress measurement, and the calibration elements comprise two polar three-piezoresistor rosettes with specific angels to calibrate the piezoresistive coefficients. The sensor and the calibration piezoresistors are etched from the SOI layer as separate “silicon islands” on the dielectric buried oxide (BOX) layer. This configuration exploits the excellent electrical insulation of the BOX layer, and enables high-temperature operation of the stress sensor by eliminating the leakage current. Design, fabrication, and the calibration of the piezoresistors at high temperatures show the feasibility of the SOI high-temperature stress sensor. The piezoresistive coefficients are calibrated versus stress and temperature, and the nonlinearity of the resistance versus temperature and the calibration errors are discussed in detail. </para>