Design automation for application-specific on-chip interconnects: A survey

Abstract

On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-Chip, particularly in data-intensive applications, where the choice of the underlying communication architecture, tailored on the particular application requirements, is critical to the global performance. This survey focuses on the design automation of a broad class of communication architectures, here referred to as structured on-chip interconnects, the predominant choice in most real-world systems. Such interconnects benefit from well-established standards, CAD compatibility, predictable performance, and are highly scalable for many types of applications. However, in spite of their importance for current MPSoCs and their recent technology advancements, the design methodologies for structured on-chip interconnects have never been exhaustively surveyed so far, unlike application-oblivious interconnect solutions like Networks-on-Chip. The essential aim of this paper is to fill this gap by presenting an extensive review of state-of-the-art design automation techniques for application-specific on-chip interconnects. The paper goes through the main options available for building different on-chip interconnect topologies, discussing the details of hierarchical buses, crossbars, and cascaded crossbars as well as the approaches that can be adopted to formalize the description of such topologies and the related parameters of interest. Then, the paper surveys the most relevant techniques proposed in the literature to analyze a given interconnect solution, i.e. quantify parameters such as latency, bandwidth, area cost, power consumption, operating frequency, followed by an in-depth review of the main approaches for interconnect synthesis, including several advanced aspects such as co-synthesis of memory and communication architectures, joint scheduling and interconnect synthesis, floorplanning, dynamic configuration, multi-path communication. After presenting the above approaches, the paper discusses the potential impact that the body of research in the area of on-chip interconnects may have on current trends and emerging interconnect technologies.