On-chip communication in the many-core era

Abstract

Electronic system design is being revolutionized by the widespread adoption of the multi- and many-core paradigms. As the number of elements on a single chip and their performance continue to increase, the communication architecture is gradually becoming the key ingredient determining various trade-offs between costs and performance: on-chip interconnects provide a vital facility for highly parallel systems, particularly in data intensive applications, where the choice of the underlying communication architecture, tailored on the particular application requirements, is critical to the whole architecture. In that respect, the first part of this thesis goes through the main options available for building different on-chip communication architectures, focusing on the design automation of structured communication architectures based on crossbars and shared buses connected through bridges. An automated methodology for optimizing many-core interconnect architectures, based on the application communication requirements, is presented. The proposed methodology turns the description of the application communication requirements into an on-chip synthesizable interconnection structure satisfying given area constraints. In addition, it could take into account possible dependencies between tasks in order to co-optimize the communication scheduling and interconnect synthesis. However, it is increasingly challenging for an electrical interconnect to meet power constraints since the power dissipation of electrical on-chip networks poorly scales with performance leading to a growing energy cost. Silicon Photonics seems to be able to empower ultra-high bandwidth with low power consumption: nanophotonic waveguides (the photonic equivalent of a wire) can achieve bandwidths in the Tb/s range, while photonic signaling consumes less power than electrical interconnects since the energy consumption necessary to send a message optically is independent of the bitrate and the distance between the two end-points with no need for power consuming repeaters, regenerators or buffers. However, designing an optical on-chip network requires addressing several challenges that have no equivalent in the electronic domain. The photonics inability to perform inflight buffering and logic suggests the use of hybrid architectures made up of a photonic circuit-switched and an electronic packet-switched networks. In this regard, in the second part of this thesis, we first propose a new power-aware path-setup protocol able to put allocated circuits on a stand-by state, rapidly recovering them when needed. Then, a novel hybrid Optical-Electronic NoC named H2ONoC is presented. Thanks to a hybrid optical topology, it is possible to achieve higher bandwidth values and constant energy dissipation regardless of the network and traffic size. Compared to previously proposed architectures, H2ONoC exhibits higher throughput, lower latency, and improved energy efficiency with heavy traffic. Therefore the main contribution of the thesis is twofold: engineering as the integration of the proposed design methods into tools to automate the interconnect design steps has direct applicability for designing multi- and many-core systems, and scientific since advanced and original communication architectures exploiting silicon photonics are presented.