Design approach to improve the performance of JAMFETs

Abstract

In this paper, the authors propose the use of electrostatic doping for n + drain region formation in Junctionless accumulation mode field effect transistors (JAMFET). This electrostatically doped drain (EDD) JAMFET employs an additional unbiased electrode (auxiliary electrode) of low workfunction on the intrinsic drain region. This technique effectively suppresses the tunneling leakage, thereby reducing I OFF by 6 orders. The tunneling of electrons from valence band of channel to conduction band of drain happens due to enhanced band bending in OFF-state (V GS = 0 V, V DS = 1 V). The presence of additional electrode in EDD-JAMFET increases the width of tunnel barrier formed at channel–drain junction in OFF-state improving the I ON/I OFF ratio by 6 orders. The gate length scaling demonstrates that leakage suppression of EDD-JAMFET is more effective with approximately 3 orders smaller I OFF even at gate length of 5 nm. The performance of graded channel device (GC-EDD-JAMFET) by electrostatic doping is also explored. Significant improvements are observed in terms of I ON/I OFF, subthreshold slope SS, DIBL and f T. Finally, the analogue parameters such as Transconductance generation factor G m/I D, Intrinsic gain A V, output conductance G D, and ‘G m/I D × f T’ performance metrics are investigated which show significant improvement at small bias current, making it suitable for ultra-low power applications.