Design and study of system on chip design for signal processing applications in terms of energy and area

Abstract

Providing flexibility into a system on a chip design is sometimes required and generally always desirable. However the cost of providing this flexibility in terms of energy consumption and silicon area is not well understood. This cost can range over many orders of magnitude depending on the architecture and implementation strategy. To quantify this cost, efficiency metrics are introduced for energy (MOPS/mW) and area (MOPS/mm2) and are used to compare a variety of designs and architectures for signal processing applications. It is found that the critical architectural parameters are the amount of flexibility, the granularity of the architecture in providing this flexibility and the amount of parallelism. A range of architectural solutions which tradeoff these parameters are presented and applied to example applications.