Design and simulation of low power flip flop in nanometer regime

Abstract

Present digital circuits demanded for low power consumption with high packaging density. Now a days scaling of MOSFET devices are goes on increasing, which causes undesirable Short Channel Effects on the device parameters, it may leads to leakage current and thereby leakage power. Current studies shows that leakage power contributes almost 40 % of the total power consumption. Hence by reducing the leakage current we can obtain a low power consumption for digital circuits in nanometer regime, but reduction in leakage power with high packaging density is the most challenging part of today’s VLSI design. In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. In this paper a CMOS Single Edge Triggered 5T Delay flip flop design with leakage reduction technique is proposed. The proposed design had several advantages in comparison with the conventional D FF in terms of reduced transistors count, decreased leakage current, etc. Then for better power reduction considered the Single Edge Triggered 5T DFF design using Self controllable Voltage Level (SVL) Technique. For further significant power reduction Body Bias technique is applied to the proposed design. The result shows a tremendous reduction in leakage power compared to the conventional 9T DFF. The design and simulations were done in 28nm technology LTspice tool.